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1. CPU SPEED FOR FPGA SIMULATION FULL
2. CPU SPEED FOR FPGA SIMULATION VERIFICATION
3. CPU SPEED FOR FPGA SIMULATION SOFTWARE

Sample C software demonstrating how well the design works, then wouldn’t it If I have to deliver a working software test bench to the customer, to include To rebuild it later in C? Why not build it in C in the first place? I mean, So, my thought was, why should I build my updated test bench in Verilog, only

CPU SPEED FOR FPGA SIMULATION FULL

A full check can’tĪt all–but that really leads to another discussion for another day. They’ll never issue concurrent read and write requests, or even multiple Further, because of the sequential nature of their design, Modules of this type set RREADY and BREADY to 1, so they’ll never test forīack pressure. (Read this address, write that address, etc.) Most Basically, the module can be used to create a form of scripted We’ve already discussed on the problems with this kind of VIP module on theīlog. This module contained a set of Verilog tasks which couldīe called to issue AXI requests to anywhere on the bus. The original test script depended upon a client-provided AXI VIP Because these tasksĪre sequential in nature, they act more like software than they do hardware. Set these wires, wait two clock ticks, etc. Unlike traditional Verilogĭesign, these tasks are written as sequential logic: wait until this happens, These tasks are essentially Verilog subroutines. Script that referenced another file containing 7.5k Verilog lines of The original test script contained about 1.2k lines of a Verilog test Peripheral(s) the module under test needed to interact with, as well as aįor the design to interact with as it might with a memory. It had a Verilog test script that drove an AXI Bus Traditional test bench structureĪs the design was given to me, the test bench had a fairly The first point is that I didn’t create it. To understand what I’m proposing, let me share a bit of the project’sīackground. So, I had a crazy thought: Why not verify the design by using a CPU within the

CPU SPEED FOR FPGA SIMULATION VERIFICATION

Of verification that cannot be done formally. The design as a whole still requires some amount With this approach is that the design as a whole is far too complicated I can get my hands on, and again I’ve had fun doing this. I’ve been known to try to formally verify everything Those who have been reading this blog know that I am a strong supporter ofįormal verification. Requires complicated instruction sequences to access it.Īt issue is, how shall such a design be tested? The device type involved is rather complex, and so the specification The controller handles multiple hardware dataĬhannels, has a scatter-gather DMA, and will (eventually) have full ECC I’m currently working on a building a basic memory controller.